New strategy can directly pattern 2D materials into high-quality wafer-scale arrays

Two-dimensional (2D) semiconductors, materials that can conduct electricity and are only a few atoms thick, are promising alternatives to the conventional silicon-based semiconductors currently used to fabricate many electronics. Despite their promise, these materials have not yet been deployed on a large scale.

One reason for this is that reliably synthesizing them and patterning them to produce wafers (i.e., circular substrates employed in the manufacturing of electronics) has so far proved challenging. In fact, many existing patterning techniques rely on chemical processes or polymer masks, both of which can leave unwanted residues on a wafer or damage the surface of 2D semiconductors.

Researchers at Nanyang Technological University recently developed a new strategy to pattern 2D films into high-quality wafer-scale arrays, without damaging them or introducing undesirable residues. Their proposed method, outlined in a paper published in Nature Electronics, entails the use of a metal stamp producing three-dimensional (3D) patterns, which can be pressed onto 2D materials to produce a wafer with desired patterns.

“2D semiconductors have the potential to replace silicon in next-generation electronic devices,” wrote Zhiwei Li, Xiao Liu and their colleagues in their paper. “However, despite advances in proof-of-concept device demonstrations and wafer-scale crystal synthesis, the lack of a compatible residue-free patterning technology has hindered industrialization. We describe a metal-stamp imprinting method for patterning 2D films into high-quality wafer-scale arrays without introducing chemical or polymer residues.”

The team’s newly devised strategy to produce wafer-scale arrays based on 2D semiconductors essentially entails pressing a metal stamp with a precisely engineered morphology onto a 2D semiconductor film that was previously grown on an underlying substrate. When the stamp is removed, specific parts of the 2D film are ‘peeled off’ from the stamp, while the rest of the film remains untouched, forming a desired pattern.

“A metal stamp with a three-dimensional morphology is used to form a local contact at the stamp–2D interface,” wrote Li, Liu and their colleagues. “The process selectively exfoliates some of the 2D material while leaving 2D arrays on the growth substrate. Microscopy and spectroscopy characterizations confirmed the clean surface and undamaged crystal structure.”

To assess the potential of their proposed metal stamp-based imprinting method, Li, Liu and their colleagues used it to create transistors (i.e., devices that control the flow of electrical current in electronics) based on the 2D material molybdenum disulfide (MoS₂). They found that their approach was effective and did not leave any undesired residues on the resulting wafers, while also being highly compatible with existing processes employed to fabricate semiconductors.

“A statistical analysis of 100 back-gated MoS₂ transistors and 500 top-gated logic circuits found a 20-times-lower variation of the threshold voltage compared to a reactive-ion-etching-based patterning process,” wrote Li, Liu and their colleagues. “The device yield on a 2-inch wafer was 97.6%.”

The new imprinting approach devised by this team of researchers could soon be refined further and used to fabricate a wide range of highly performing electronics based on 2D semiconductors. Concurrently, other electronics engineers could draw inspiration from this approach and devise similar promising strategies for the fabrication of reliable devices based on 2D semiconductors, which might collectively contribute to the future replacement of existing silicon semiconductors.

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